1. Field of the Invention
The present invention generally relates to the forming of capacitors in integrated circuits, and in particular the forming of capacitors associated with sram cells.
2. Discussion of the Related Art
FIG. 1 shows an SRAM cell circuit with six transistors. The cell includes a memory point formed of two inverters I1 and I2 connected head-to-tail and having their two inputs, respectively BLTI, BLFI, connected to bit lines BLT, BLF by N-channel MOS transistors (NMOS) T1, T2. The gates of transistors T1 and T2 are connected to a word line WL. Inverter I1 comprises a PMOS transistor TP1 and an NMOS transistor TN1. The gates of transistors TP1 and TN1 are connected to terminal BLTI of the inverter. The drains of transistors TP1 and TN1 are connected and form the output terminal of the inverter. The sources of transistors TP1 and TN1 are respectively connected to a supply voltage VDD and a ground GND. Inverter I2 has the same structure and includes a PMOS transistor TP2 and an NMOS transistor TN2.
FIG. 2 shows a simplified top view of an embodiment in CMOS technology of the SRAM cell of FIG. 1. For simplicity, the P- and N-channel transistors are shown with the same gate widths. N-channel transistors T1, T2, TN1, and TN2 are formed in a P-type substrate (SUB) and P-channel transistors TP1 and TP2 are formed in an N-type well (NWELL). The drain regions of transistors TN1, T1, and TN2, T2 are confounded. The transistor gates, formed of polysilicon, are shown in hatchings. The gates of transistors TP1, TN1, respectively TP2, TN2, are interconnected. The drains of transistors TP1 and TN1 are connected to the gates of transistors TP2, TN2 by a conductive line formed in an upper metal layer (METAL1) via vias or contacts (the locations of which are shown with crosses). The drains of transistors TP2 and TN2 are connected to the gate of transistors TP1, TN1 by a conductive line formed in the same metal layer (METAL1). Vias form the contact between the source regions of transistors T1, T2, TN1, TN2, TP1, TP2 and metal lines, not shown, respectively connected to lines BLT, BLF and to voltages GND, GND, VDD, and VDD. The N-type well is grounded and the substrate is at a predetermined voltage. For clarity, the STI transistor insulation trenches have not been shown. The STI trenches are preferably the inverse of the active areas (drains or sources).
Inverters I1 and I2 form a bistable structure or memory point that can take two states. When transistors T1 and T2 are on, an appropriate control of bit lines BLT, BLF enables modifying the state of the memory point and thereby programming a piece of information. When transistors T1 and T2 are off, the memory cell keeps the information in the form of a charge on the gate capacitors of the transistors of one or the other of the inverters.
If an ionizing radiation hits cell 2, this creates parasitic electric charges that may change the stored state. Because recent SRAM cells are formed with MOS transistors having smaller and smaller dimensions, the gate capacitance of the transistors forming the inverters is smaller and smaller and the memory point is more and more sensitive to ionizing radiations, all the more as supply voltage VDD of the inverters is smaller and smaller.
To increase the resistance against ionizing radiations of an SRAM cell of small surface area formed with small-size transistors, it has been provided to couple the gates of the memory point transistors with additional capacitors. The problem of forming such capacitors without increasing the SRAM cell surface area then has to be overcome.